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RT8023 1 ds8023-03 march 2011 www.richtek.com ordering information applications z portable instruments z microprocessors and dsp core supplies z cellular phones z wireless and dsl modems z pc cards z digital cameras 1.2mhz 1.5a synchronous step-down converter with two ldos general description the RT8023 combines two low dropout (ldo) linear regulators and a step-down converter with an input voltage range of 2.6v to 5.5v. each output voltage is adjustable from 0.8v to 5v. with independent enable and power- good pins for each regulator, it is easy to control the power up sequence, which is important in some applications. the ldo has an independent input and is capable of delivering up to 700ma(ldo1) and 350ma(ldo2 ) output currents with ultra-low dropout. the ldo has high psrr and can work with low-esr space saving ceramic capacitors. all these make it ideal for portable rf and wireless applications with demanding performance and space requirements. other features include high output accuracy, current limiting protection, and 40 s fast turn- on time. the step-down converter is a 1.2mhz pwm, current mode converter. its high switching frequency allows the use of tiny, low cost capacitors and inductors 2mm or less in height. internal power switches with low on-resistance increase efficiency and eliminate the need for external schottky diodes. the converter can run at 100% duty cycle for low dropout operation that extends battery life in portable systems. features z z z z z converter input voltage range : 2.6v to 5.5v, ldo input voltage range : 2.4v to 5.5v z z z z z low-noise ldo for rf application z z z z z ultra-fast response in line/load transient z z z z z ldo turn-on time less than 40us z z z z z only 1 f ldo output capacitor required for stability z z z z z current limiting protection z z z z z 1.5a, high efficiency step-down converter z z z z z 1.2mhz constant switching frequency z z z z z low r ds(on) internal switches z z z z z no schottky diode required z z z z z 0.8v reference allows low output voltage z z z z z low dropout operation : 100% duty cycle internally compensated z z z z z < 2 a shutdown current z z z z z power good output voltage monitor z z z z z internal soft-start for pwm converter z z z z z easy power sequence control z z z z z over temperature protection z z z z z short circuit protection z z z z z thermally enhanced 24-lead wqfn package z z z z z rohs compliant and 100% lead (pb)-free note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. package type qw : wqfn-24l 4x4 (w-type) RT8023 lead plating system p : pb free g : green (halogen free and pb free)
RT8023 2 ds8023-03 march 2011 www.richtek.com typical application circuit pin configurations (top view) wqfn-24l 4x4 figure 1. 1.2v output step-down converter and dual 2.5v output regulators note : must to use ceramic x5r/x7r capacitors. pgood1 vdd1 vin1 vin1 vin1 pgnd fb3 pgood3 en3 en2 pgood2 fb2 vout2 nc phase1 phase1 vin2 nc vin3 agnd en1 fb1 nc vout3 1 2 3 4 5 6 7 21 20 19 18 17 16 15 8 9 10 12 14 13 24 22 23 11 pgnd 25 vdd1 vout2 fb2 vin1 pgood3 en1 RT8023 1 6, exposed pad (25) 17 11 13 vout3 fb3 pgood1 12 15 phase1 16 8, 9 vin3 pgnd 14 20 18 3, 4, 5 r9 425k r10 200k c7 1f r8 200k r7 425k c6 1f pgood2 c4 1f vin2 c3 1f r5 100k r6 100k c2 0.1f r1 100 r2 100k en2 en3 fb1 r3 100k r4 200k l1 2.2h c5 22uf v in1 pgood1 en1 en2 en3 v out1 1.2v/1.5a v in2 v in3 pgood2 pgood3 v out2 2.5v/0.7a v out3 2.5v/0.35a 2 21 23 24 c1 10f agnd 19
RT8023 3 ds8023-03 march 2011 www.richtek.com functional pin description pin no. pin n ame pin function 1 pgood1 power good indicator of step-down converter. open-drain lo g ic output that is opened when the output voltage exceeds 90% of the regulation point. 2 vd d1 signal input supply. decouple this pin to gnd with a capacitor. normall y vin1 is equal to vdd1. keep the volta g e difference between vdd1 and vin1 less than 0.5v. 3, 4, 5 vin1 power input supply of step-down converter. decouple this pin to gnd with a capacitor. 6, 25 (e xposed p ad) pgnd power ground. must be soldered to pcb g round for electrical contact and optimum thermal performance. the exposed pad must be soldered to a lar g e pcb and connected to pgnd for maximum power dissipation. 8, 9 phase1 internal power mosfet switches output of step-down converter. connect this pin to the inductor. 11 vin 2 power input supply of ldo1. decouple this pin to gnd with a 1uf or g reater capacitor. 12 vout2 output of ldo1. a 1uf or greater output low-esr ceramic capacitor is required for stability.. 13 fb2 feedback pin of ldo1. receives the feedback volta g e from a resistive divider connected across the output. 14 pgood2 power good indicator of ldo1. open-drain lo g ic output that is opened when the output voltage exceeds 90% of the regulation point. 15 en2 ldo1 enable. a logical high level at this pin enables ldo1, while a lo g ical low level causes ldo1 to shut down. 16 en3 ldo2 enable. a lo g ic hi g h level at this pin enables ldo2, while a lo g ic low level causes ldo2 to shut down. 17 pgood3 power good indicator of ldo2. open-drain lo g ic output that is opened when the output voltage exceed 90% of regulation point. 18 fb3 feedback pin of ldo2. receives the feedback volta g e from a resistive divider connected across the output. 19 agnd analog grand. all small-signal of the ic should connect to this g round, which connects to pgnd at one point for away exposed pad. 20 vout3 output of ldo2. a 1uf or greater output low-esr ceramic capacitor is required for stability. 21 vin3 power input supply of ldo2. decouple this pin to gnd with a 1uf or g reater capacitor. 7, 10, 22 nc no internal connection. 23 fb1 feedback pin of step-down converter. receives the feedback volta g e from a resistive divider connected across the output. 24 en1 step-down converter enable. a logic high level at this pin enables step-down converter, while a logic low level causes step-down converter to shut down.
RT8023 4 ds8023-03 march 2011 www.richtek.com function block diagram driver control logic 0.72v 0.4v oc limit isen slope compensation osc output clamp ea 0.8v internal- soft start por fb1 vin1 vdd1 pgood1 gnd phase1 otp vref2 vref3 vin2 current limit fb3 ea vout3 0.8v 0.72v vin3 current limit fb2 ea vout2 0.8v 0.72v pgood3 ot por pgood2 en1 en2 en3
RT8023 5 ds8023-03 march 2011 www.richtek.com absolute maximum ratings (note 1) z s upply input voltage, vin1, vin2 ----------------------------------------------------------------------------- ? 0.3v to 6v z output pin v oltage ------------------------------------------------------------------------------------------------ ? 0.3v to (v in1 + 0.3v) z phase pin v oltage ---------------------------------------------------------------------------------------------- ? 0.3v to (v in2 + 0.3v) z other i/o pin v oltages ------------------------------------------------------------------------------------------- ? 0.3v to 6v z power dissipation, p d @ t a = 25 c wqfn-24l 4x4 ---------------------------------------------------------------------------------------------------- 1.923w z package thermal resistance (note 2) wqfn-24l 4x4, ja ----------------------------------------------------------------------------------------------- 52 c/w wqfn-24l 4x4, jc ---------------------------------------------------------------------------------------------- 7 c/w z junction temperature --------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ---------------- ------------------------------------------------------- 260 c z storage temperature range ------------------------------------------------------------------------------------ ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) -------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ---------------------------------------------------------------------------------------------- 200v electrical characteristics (t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit step-down converter input voltage range v in1 2.6 -- 5.5 v feedback voltage v fb1 0.784 -- 0.816 v v dd1 rising 2.24 2.36 2.48 v under voltage lockout threshold v uvlo v dd1 hysteresis -- 150 -- mv dc bias current active, v fb = 0.75v, not switching -- 300 -- a shutdown current i shdn en2 = 0 -- -- 2 a switch on resistance, high r fet_h i phase = 0.5a -- 150 270 m switch on resistance, low r fet_l i phase = 0.5a -- 90 150 m peak current limit i lim 1.7 2.3 3.2 a switching frequency 1 1.2 1.4 mhz output voltage line regulation v in1 = 2.6v to 5.5v -- 0.01 1 %/v to be continued recommended operating conditions (note 4) z supply input voltage, converter ------------------------------------------------------------------------------- 2.6v to 5.5v z supply input voltage, ldos ------------------------------------------------------------------------------------ 2.4v to 5.5v z junction temperature range ------------------------------------------------------------------------------------ ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------------ ? 40 c to 85 c
RT8023 6 ds8023-03 march 2011 www.richtek.com parameter symbol test conditions min typ max unit output voltage load regulation measured by sever loop, ea output from 0.253v to 0.853v -- 0.01 1 % fb threshold for pgood transition 0.68 0.72 0.76 v pgood1 pull-down resistance -- -- 100 en1 input high 1.4 -- -- v en1 input low -- -- 0.4 v thermal shutdown temperature t sd (note 5) -- 145 -- thermal shutdown hysteresis t sd -- 25 -- c ldo1 (v in = v out + 0.5v, v en = vi in , c in = c out = 1uf (ceramic)) input voltage range v in2 2.4 -- 5.5 v feed back voltage v fb2 0.784 -- 0.816 v output noise voltage e no v out2 = 1.5v, i out2 = 1ma -- 30 -- v rms quiescent current i q v en2 = 5v, i out2 = 0ma -- 35 60 a shutdown current i shdn en2 = 0 -- -- 2 a en2 pin current i en2 measured en leakage current. en2 = 5.5v -- 0.1 1 a current limit i lim r load = 0 0.7 0.9 1.2 a dropout voltage v drop i out2 = 500ma, v in2 > 2.7v -- 250 400 mv load regulation v load 1ma < i out2 < 500ma, v in2 > 2.7v -- 1 -- % line regulation v line v in2 = (v out2 + 0.5) to 5.5v i out2 = 1ma -- 0.01 0.2 %/v power supply rejection ratio, f = 100khz psrr i out2 = 300ma -- 40 -- db fb threshold for pgood transition -- 0.72 0.76 v pgood2 pull-down resistance -- -- 120 en2 input high 1.4 -- -- v en2 input low -- -- 0.4 v ldo2 (v in = v out + 0.5v, v en = v in , c in = c out = 1uf (ceramic)) input voltage range v in3 2.4 -- 5.5 v feed back voltage v fb3 0.784 -- 0.816 v output noise voltage e no v out3 = 1.5v, i out3 = 1ma -- 30 -- v rms quiescent current i q v en3 = 5v, i out3 = 0ma -- 35 60 a shutdown current i shdn en1 = 0 -- -- 2 a en3 pin current i en3 measured en leakage current. en3 = 5.5v -- 0.1 1 a to be continued
RT8023 7 ds8023-03 march 2011 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective four layers thermal conductivity test board of jedec 51-7 thermal measurement standard. the case point of jc is on the expose pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. the power source for thermal shutdown circuit must be provided by v in1 . there must be a power input into ldo1 and then the ldo2 can provide the thermal shutdown function. parameter symbol test conditions min typ max unit current limit i lim r load = 0 0.35 0.48 0.6 a dropout voltage v drop i out3 = 250ma, v in3 > 2.7v -- 250 400 mv load regulation v load 1ma < i out3 < 250ma, v in3 > 2.7v -- 1 -- % line regulation v line v in3 = (v out3 + 0.5) to 5.5v i out3 = 1ma -- 0.01 0.2 %/v en3 pin current i en3 measured en leakage current. en3 = 5.5v -- 0.1 1 a current limit i lim r load = 0 0.35 0.48 0.6 a dropout voltage v drop i out3 = 250ma, v in3 > 2.7v -- 250 400 mv load regulation v load 1ma < i out3 < 250ma, v in3 > 2.7v -- 1 -- % line regulation v line v in3 = (v out3 + 0.5) to 5.5v i out3 = 1ma -- 0.01 0.2 %/v power supply rejection ratio, f = 100khz psrr i out3 = 150ma -- 40 -- db fb3 threshold for pgood transition -- 0.72 0.76 v pgood3 pull-down resistance -- -- 120 en3 input high 1.4 -- -- v en3 input low -- -- 0.4 v
RT8023 8 ds8023-03 march 2011 www.richtek.com typical operating characteristics buck output voltage vs. load current 1.196 1.197 1.198 1.199 1.200 1.201 1.202 1.203 0 0.15 0.3 0.45 0.6 0.75 0.9 1.05 1.2 1.35 1.5 load current (a) output voltage (v) v out1 = 1.2v v in1 = 3.3v v in1 = 5.5v buck efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 output current (a) efficiency (%) v out1 = 1.2v v in1 = 3.3v v in1 = 5v buck output voltage vs. temperature 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 -50 -25 0 25 50 75 100 125 temperature output voltage (v) ( c) v out1 = 1.2v v in1 = 3.3v v in1 = 5.5v ( c) buck current limit vs. temperature 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 -50 -25 0 25 50 75 100 125 temperature current limit (a) v out1 = 1.2v v in1 = 3.3v v in1 = 5.5v buck frequency vs. input voltage 1.00 1.05 1.10 1.15 1.20 1.25 1.30 -50 -25 0 25 50 75 100 125 input voltage (v) frequency (mhz ) v out1 = 1.2v, i out1 = 0.1a v in1 = 3.3v v in1 = 5.5v buck frequency vs. input voltage 1.00 1.05 1.10 1.15 1.20 1.25 1.30 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) frequency (mhz) v out1 = 1.2v, i out1 = 0.1a
RT8023 9 ds8023-03 march 2011 www.richtek.com v in1 = 5v, v out1 = 1.2v i out1 = 0a to 1.5a buck load transient response time (50 s/div) i out1 (1a/div) v out1 (50mv/div) v in1 = 3.3v, v out1 = 1.2v, i out1 = 1.5a buck pgood response time (100 s/div) i out1 (0.5a/div) v out1 (500mv/div) v en1 (2v/div) v pgood1 (2v/div) ldo1 dropout voltage vs. load current 0 100 200 300 400 500 600 0 100 200 300 400 500 600 700 load current (ma) dropout voltage (mv) t a = -40 c t a = 25 c t a = 125 c v out2 = 2.5v ldo2 dropout voltage vs. load current 0 100 200 300 400 500 600 0 50 100 150 200 250 300 350 load current (ma) dropout voltage (mv) t a = -40 c t a = 25 c t a = 125 c v out3 = 2.5v v in1 = 3.3v, v out1 = 1.2v, i out1 = 1.5a buck power on from en time (100 s/div) i in1 (0.5a/div) v out1 (500mv/div) v en1 (2v/div) v in1 = 3.3v, v out1 = 1.2v i out1 = 1.5a buck switching waveforms time (1 s/div) i phase1 (500ma/div) v out1 (5mv/div) v phase1 (5v/div) i phase1
RT8023 10 ds8023-03 march 2011 www.richtek.com ldo1 current limit vs. input voltage 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 2.533.544.555.5 input voltage (v) current limit (a) v out2 = 2.5v ldo2 current limit vs. input voltage 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 2.533.544.555.5 input voltage (v) current limit (a) v out3 = 2.5v ldo1 current limit vs. temperature 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 -50 -25 0 25 50 75 100 125 temperature current limit (a) v out2 = 2.5v v in2 = 3.3v v in2 = 5.5v ( c) ldo2 current limit vs. temperature 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 -50 -25 0 25 50 75 100 125 temperature current limit (a) v out3 = 2.5v v in3 = 3.3v v in3 = 5.5v ( c) ldo1 output voltage vs. load current 2.480 2.485 2.490 2.495 2.500 2.505 2.510 2.515 2.520 0 100 200 300 400 500 600 700 load current (ma) output voltage (v) v out2 = 2.5v v in2 = 3.3v v in2 = 5.5v ldo2 output voltage vs. load current 2.490 2.495 2.500 2.505 2.510 2.515 2.520 2.525 2.530 0 50 100 150 200 250 300 350 load current (ma) output voltage (v) v out3 = 2.5v v in3 = 3.3v v in3 = 5.5v
RT8023 11 ds8023-03 march 2011 www.richtek.com v in3 = 2.5v to 3.5v, v out3 = 1.2v, i out3 = 100ma ldo2 line transient response time (50 s/div) v out3 (50mv/div) v in3 (1v/div) v in2 = 2.5v to 3.5v, v out2 = 1.2v, i out2 = 100ma ldo1 line transient response time (50 s/div) v out2 (50mv/div) v in2 (1v/div) v in3 = 5v, v out3 = 1.2v i out3 = 0a to 0.35a ldo2 load transient response time (50 s/div) i out3 (0.2a/div) v out3 (20mv/div) v in2 = 5v, v out2 = 1.2v i out2 = 0a to 0.7a ldo1 load transient response time (50 s/div) i out2 (0.5a/div) v out2 (20mv/div) ldo2 output voltage vs. temperature 2.47 2.48 2.49 2.50 2.51 2.52 2.53 -50 -25 0 25 50 75 100 125 temperature output voltage (v) v in3 = 3.3v, v out3 = 2.5v ( c) ( c) ldo1 output voltage vs. temperature 2.47 2.48 2.49 2.50 2.51 2.52 2.53 -50 -25 0 25 50 75 100 125 temperature output voltage (v) v in2 = 3.3v, v out2 = 2.5v
RT8023 12 ds8023-03 march 2011 www.richtek.com v in2 = 4.5v, v out2 = 1.5v, i out2 = 300ma ldo1 noise time (10ms/div) v out2 (50uv/div) v in3 = 4.5v, v out3 = 1.5v, i out3 = 300ma ldo2 noise time (10ms/div) v out3 (50uv/div) ldo1 psrr -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 100000 1000000 frequency (hz) psrr (db) v in2 = 2.5v to 2.6v, v out2 = 1.5v i out = 10ma i out = 300ma 0.01 0.1 1 10 100 1000 (khz) crosstalk -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 100000 1000000 frequency (hz) crosstalk (db) v in2 to v out3 , i out3 = 10ma 0.01 0.1 1 10 100 1000 (khz) ldo1 v in2 = 2.5v to 2.6v ldo2 v out3 = 1.5v v in3 = 5v, v out3 = 1.2v, i out3 = 0.3a ldo2 power on from en3 time (10 s/div) i in3 (0.5a/div) v out3 (500mv/div) v en3 (5v/div) v in2 = 5v, v out2 = 1.2v, i out2 = 0.3a ldo1 power on from en2 time (10 s/div) i in2 (0.5a/div) v out2 (500mv/div) v en2 (5v/div)
RT8023 13 ds8023-03 march 2011 www.richtek.com v in3 = 5v, v out3 = 1.2v, i out3 = 0.3a ldo2 pgood response time (25 s/div) i out3 (0.5a/div) v out3 (500mv/div) v en3 (5v/div) v pgood (2v/div) v in2 = 5v, v out2 = 1.2v, i out2 = 0.3a ldo1 pgood response time (25 s/div) i out2 (0.5a/div) v out2 (500mv/div) v en2 (5v/div) v pgood (2v/div)
RT8023 14 ds8023-03 march 2011 www.richtek.com application information for buck converter part the typical application circuit shows the basic RT8023 application circuit. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . inductor selection the inductor value and operating frequency determine the ripple current according to a specific input and output voltage. the ripple current i l increases with higher v in and decreases with higher inductance. out out l in vv i = 1 fl v ??? ? ?? ??? ? ??? ? having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. high frequency with small ripple current can achieve highest efficiency operation. however, it requires a large inductor to achieve this goal. for the ripple current selection, the value o f i l = 0.4(i max ) will be a reasonable starting point. the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : out out l(max) in(max) vv l = 1 fi v ??? ? ? ??? ? ??? ? inductor core selection the inductor type must be selected once the value for l is known. generally speaking, high efficiency converters can not afford the core loss found in low cost powdered iron cores. so, the more expensive ferrite or mollypermalloy cores will be a better choice. the selected inductance rather than the core size for a fixed inductor value is the key for actual core loss. as the inductance increases, core losses decrease. unfortunately, increase of the inductance requires more turns of wire and therefore the copper losses will increase. ferrite designs are preferred at high switching frequency due to the characteristics of very low core losses. so, design goals can focus on the reduction of copper loss and the saturation prevention. ferrite core material saturates ? hard ? , which means that inductance collapses abruptly when the peak design current is exceeded. the previous situation results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate energy. however, they are usually more expensive than the similar powdered iron inductors. the rule for inductor choice mainly depends on the price vs. size requirement and any radiated field/ emi requirements. c in and c out selection the input capacitance, c in, is needed to filter the trapezoidal current at the source of the top mosfet. to prevent large ripple current, a low esr input capacitor sized for the maximum rms current should be used. the rms current is given by : out in rms out(max) in out v v i = i 1 vv ? this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c out is determined by the required effective series resistance (esr) to minimize voltage ripple. moreover, the amount of bulk capacitance is also a key for c out selection to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by : out l out 1 viesr 8fc ?? ?? + ?? ??
RT8023 15 ds8023-03 march 2011 www.richtek.com the output ripple will be highest at maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirement. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr value. however, it provides lower capacitance density than other types. although tantalum capacitors have the highest capacitance density, it is important to only use types that pass the surge test for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr. however, it can be used in cost-sensitive applications for ripple current rating and long term reliability considerations. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. output voltage programming the resistive divider allows the fb pin to sense a fraction of the output voltage as shown in figure2. RT8023 gnd fb r1 r2 v out figure 2. setting the output voltage for adjustable voltage mode, the output voltage is set by an external resistive divider according to the following equation : out ref r1 v = v 1 r2 ?? + ?? ?? where v ref is the internal reference voltage (0.8v typ.). efficiency consideration the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. the efficiency can be expressed as : efficiency = 100 ? (l1 + l2 + l3 + ?..) where l1, l2, etc., are the individual losses as a percentage of input power, although all dissipative elements in the circuit produce losses, v in quiescent current and i 2 r losses are two main sources for most of the losses. the v in quiescent current loss dominates the efficiency loss at a very low load current whereas the i 2 r loss dominates the efficiency loss at medium to high load current. in a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. the v in quiescent current appears due to two factors including the dc bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge q moves from v in to ground. the value of q/ t is the current out of v in that is typically larger than the dc bias current. in continuous mode, i gatechg = f(q t + q b ) where q t and q b are the gate charges of the internal top and bottom switches. both the dc bias and gate charge losses are proportional to v in and their effects will be more significant at higher supply voltages.
RT8023 16 ds8023-03 march 2011 www.richtek.com 2. i 2 r losses are calculated from the resistance of the internal switches r sw and external inductor r l . in continuous mode, the average output current flowing through inductor l is ? chopped ? between the main switch and the synchronous switch. thus, the series resistance looking into the lx pin is a function of both top and bottom mosfets r ds(on) and the duty cycle (dc) as follows : r sw = r ds(on)top x dc + r ds(on)bot x (1 ? dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristic curves. thus, to obtain i 2 r loss, simply add r sw to r l and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% of total losses. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr) also begins to charge or discharge c out generating a feedback error signal for the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. for ldo part the external capacitors used with the RT8023 must be carefully selected for regulator stability and performance just like any low-dropout regulator. using a capacitor whose value is >1 f on the RT8023 input and the amount of capacitance can be increased without limit. the input capacitor must be located at a distance of not more than 1cm from the input pin of the ic and returned to a clean analog ground. any good quality ceramic or tantalum can be used for this capacitor. the capacitor with larger value and lower esr (equivalent series resistance) provides better psrr and line-transient response. the output capacitor must meet both requirements for minimum amount of capacitance and esr in all ldo applications. the RT8023 is designed specifically to work with low esr ceramic output capacitor for space-saving and performance consideration. enable the RT8023 goes into sleep mode when the en pin is in the logic low condition. the RT8023 has an en pin to turn on or turn off the regulator during this condition. when the en pin is in the logic high condition, the regulator will be turned on. the typical supply current for the en pin is 0.1 a. the en pin may be directly tied to v in to keep the part on. the enable input is cmos logic and can not be left floating. current limit the RT8023 contains an independent current limiter to monitor and control the pass transistor's gate voltage. the part limits the two ldos' current respectively as follows : ldo1 : 700ma and ldo2 : 350ma (min.). the output can be shorted to ground indefinitely without damaging the part. pgood the power good output is an open-drain output. it is designed essentially to work as a power-on reset generator once the regulated voltage was up or a fault condition occurs. the output of the power good drives to low when a fault condition occurs. the power good output will be driven back to up once the output reaches 90% of its nominal value. the output voltage level will be drooped at the fault condition including current limit, thermal shutdown or shutdown and triggers the pgood detector to alarm a fault condition. due to the shutdown mode condition, a fault condition occurs by pulling up the pgood output low. and it will sink a current from the open drain and the external power. it is recommended to select a suitable pulling resistance to achieve the goal of ideal power dissipation control. psrr the power supply rejection ratio (psrr) is defined as the ability of a regulator to maintain its output voltage as its power supply voltage is varied. the psrr is found to be: psrr = 20 x log[ v out / v in ]
RT8023 17 ds8023-03 march 2011 www.richtek.com thermal consideration for continuous operation, do not exceed the maximum operation junction temperature 125 c. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = (t j(max) ? t a )/ ja where t j(max) is the maximum operating junction temperature 125 c, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of RT8023, where t j(max) is the maximum junction temperature of the die (125 c) and t a is the maximum ambient temperature. the junction to ambient thermal resistance ja is layout dependent. for wqfn-24l 4x4 packages, the thermal resistance ja is 52 c/w on the standard jedc 51-7 four-layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / 52 c/w = 1.923 for wqfn-24l 4x4 packages. the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja for RT8023 packages, the figure 6 of derating curves allows the designer to see the effect of rising ambient temperature of maximum power allowed. figure 3 figure 4 note : the temperature effect must be taken into consideration for heavy load psrr measuring. figure 5. the psrr for the RT8023 how a pcb layout will affect the psrr is shown as figure 3. if the fb is placed in parallel with the pgood and en, the output voltage will be interfered to result in a bad psrr performance that is shown as figure 5. for the layout as shown in figure 4, the fb is separated from the pgood and the en. in this condition, there will be less interference for the output voltage and it will lead to a better psrr performance. as shown in figure 5, if the fb is separated from the pgood and en and a gnd path is added, then it will lead to a better psrr performance especially for high frequency applications. en3 fb2 pgood2 fb3 pgood3 en2 gnd gnd gnd path gnd paht vout vout en3 fb2 pgood2 fb3 pgood3 en2 gnd gnd vout vout ldo1 psrr -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 100000 1000000 frequency (hz) psrr (db) v out = 1.5v, i out = 10ma 0.01 0.1 1 10 100 1000 (khz) figure 3 figure 4 without gnd path figure 4 with gnd path
RT8023 18 ds8023-03 march 2011 www.richtek.com layout consideration follow the pcb layout guidelines for optimal performance of rt 8023 ` please refer to the psrr section for layout improvement. ` keep the traces of the main current paths as short and wide as possible. ` put the input capacitor as close as possible to the device pins (vin and gnd). ` lx node is with high frequency voltage swing and should be kept small area. keep analog components away from lx node to prevent stray capacitive noise pick-up. ` connect feedback network behind the output capacitors. keep the loop area small. place the feedback components near the RT8023. for the ldo layout part, put the output capacitor as close as possible to the device pins. (vin and gnd). ` connect all analog grounds to a command node and then connect the command node to the power ground behind the output capacitors. figure 7 v in3 v in1 v out1 pgood1 vdd1 vin1 vin1 vin1 pgnd fb3 pgood3 en3 en2 pgood2 fb2 vout2 nc phase1 phase1 vin2 nc vin3 agnd en1 fb1 nc vout3 1 2 3 4 5 6 7 21 20 19 18 17 16 15 8910 12 14 13 24 22 23 11 pgnd 25 v out3 v in2 c1 c2 c3 c4 c5 c6 c7 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 l1 the resistive dividers r3, r4, r7, r8, r9 and r10 must be located as close to the fb pin as possible. input capacitors c3, c4 and output capacitors c6, c7 must be located at a distance of not more than 1cm from RT8023 to gnd. the phase1 trace must be wide and short, keep sensitive components away from this trace. keep output capacitor c5 near the ic. put input capacitor as dose as possible to v in1 and gnd pins. figure 6. derating curves for RT8023 packages 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) wqfn-24l 4x4
RT8023 19 ds8023-03 march 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com a a1 a3 d e d2 e2 l b e 1 see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 3.950 4.050 0.156 0.159 d2 2.300 2.750 0.091 0.108 e 3.950 4.050 0.156 0.159 e2 2.300 2.750 0.091 0.108 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 24l qfn 4x4 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2 outline dimension

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